A Low Noise Amplifier (LNA) designed in IHP SG13G2 BiCMOS technology achieving 5.77 dB noise figure at 160 GHz with 27 GHz bandwidth (146-173 GHz) and 12.5 dB peak gain.

A DC to 40 GHz Single Ended Transimpedance Amplifier (TIA) in IHP SG13G2 BiCMOS technology optimized for low input-referred current noise density of ~9.5 pA/√Hz.

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

A simple MOSFET model with only 5-DC-parameters for circuit simulation

This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.

Fully-differential asynchronous non-binary 12-bit SAR-ADC

Reinforcement learning assisted analog layout design flow.

SRAM build space for SKY130 provided by SkyWater.

SKY130A implementatoin of the Blake2s hash algorithm

Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130

AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP

Design of LDO using open source SKY130PDK

Design of miller compensated 2 stage opamp using open source SKY130PDK

A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the front-end Gm-cell and a mixed-signal simulation w/ Ngspice.

Automated generation of a PMIC

Mixed Signal Circuit Design and Simulation Marathon under very Good category Article: https://www.linkedin.com/pulse/mixed-signal-simulation-marathon-using-esim-sky130-kannan-moudgalya/?trackingId=PLrgw35VThqQ5QB

A folded-cascode OTA with 3.3V power supply and 54.27 dB DC gain with 66.8MHz unity frequency

Attempt at 24-bit (RGB888) VGA DAC

TT07 resub of tt04-raybox-zero "3D" VGA ray caster demo (like Wolf3D)

Complete RTL-to-GDSII flow for 32-tap FIR filter on SKY130 130nm — 33% fewer cells than OpenLane, formally verified (SAT proof), DRC/LVS clean

PTAT bias current source for sky130nm

This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop

8-bit Succesive approximation register analog to digital converter (SAR-ADC)

Design of a common source amplifier using Skywater sky130 technology

2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)

CMOS circuit design and SPICE simulation study covering NMOS behavior, inverter VTC, noise margins, and robustness analysis.

This project implements a tetrahedral oscillator inspired by the paper “Analysis and Design of a Tetrahedral Oscillator” by Richelle L. Smith and Thomas H. Lee. The oscillator is built from coupled inverter pairs, and its operating frequency is tuned by adding capacitive loads to the internal nodes.

Repository for open-source tools to VLSI design

Advanced SRAM Controller with ECC Support for Sky130 Process - Production-Ready Multi-Port Memory System.

Mixed-signal FIR accelerator SoC on Caravel/Sky130A — CIC decimator, 8-tap programmable FIR filter, PWM DAC, Wishbone CSR

OpenLane2 example project for integrating an SRAM hard macro and generating GDS.

IEEE Summer School on Semiconductor Devices & Integrated Circuits 2025 por Nanociencias y Micro y Nanotecnologías del Instituto Politécnico Nacional

A synthesizable RISC-V processor ecosystem in SystemVerilog. Features 32/64-bit single-cycle and 5-stage pipelined architectures, ASIC-proven on Sky130.

8 bit RISC Processor for SKY 130nm process

A complete 1×3 NoC router implemented from RTL to GDSII using the Sky130A PDK. Includes full functional verification, synthesis (Yosys), and physical design using OpenLane/OpenROAD, culminating in a signoff-clean GDS layout.

Hands-on open-source ASIC design portfolio documenting the complete RTL-to-GDSII flow, SoC verification, and gate-level simulation using OpenLane, OpenROAD, SKY130, Caravel, and VSDSquadron.

RISC-V Reference SoC Design and Tapeout Program Phase 2 personal documentation

Analog experiements, targetting sky26a, double oscillators

This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop.

Aurora v1 — a complete RISC-V + tensor-accelerator AI SoC taken from RTL to signed-off GDSII with open-source tools (Sky130B). Timing MET, DRC=1, LVS device-match.

IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.

An open-source 32-bit RISC-V MCU designed for IHP SG13G2 130nm BiCMOS technology. Features a PicoRV32 core, QSPI XIP, and a rich peripheral set for low-power IoT and embedded control.

Voltage Controlled Oscillator that produces 1GHz output frequency at voltage 3.3V using IHP PDK as a part of eSim Marathon

Low-power mmWave IP portfolio on IHP SG13G2 SiGe BiCMOS — V-band LNA, VCO, and PA driver

SRAM macros created for the GF180MCU provided by GlobalFoundries.

SRAM build space for the GF180MCU provided by GlobalFoundries.

KianV GF180 ASIC runs ulinux, linux and XV6

Open source sillicon for a 100Mbps 3 port unmanaged cut-though ethernet switch

Beginner-friendly, Docker-based starter kit for designing a GF180MCU chip from RTL to a manufacturable GDSII — simulate, verify, and harden a working example, then make it yours and submit it to a wafer.space shuttle.

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

VeeR EH1 core

VeeR EL2 Core

Parametric AXI4 crossbar in SystemVerilog

Open Application-Specific Instruction Set processor tools (OpenASIP)

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Quasar 2.0: Chisel equivalent of SweRV-EL2

RISCV CPU implementation in SystemVerilog

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1

In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)

Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

Synthesizable SystemVerilog IP-Core of the I2S Receiver

The Voyager flight computer on SKY130 silicon. 58 cells. Currently 24 billion km away.

"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"

Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host interface, and fused streaming datapath. Validated on chest X-ray pneumonia detection. Silicon Sprint 2026 — AUC.

The world's first probabilistic processor. Distributions are the data type. Bayesian inference is a machine instruction. 2,237 SKY130 gates.

Quantum circuit accelerator on classical silicon. 8 qubits, 238 gates, 200MHz. Because irony is a valid design methodology.

LLM inference SoC

MATLAB code for the lab sessions in the "ASIC for DSP" course at LiU-ISY

EVPIX-RV32: 5-Stage Custom RISC-V SoC with Integrated IPU and TinyML Support for Real-Time Edge-Vision AI Acceleration: RTL-to-GDSII Design, Verification, Basys-3 Artix-7 FPGA Prototyping and SkyWater 130-nm CMOS ASIC was implementation

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

Base-12 arithmetic in silicon. 182 SKY130 gates. The Mesopotamians were right.

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

Arm Cortex-M0 based Customizable SoC for IoT Applications

32-bit RISC-V microcontroller

An example project that utilizes caravel user space for an ibex based SoC

FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already installed and ready to use.

https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

This repository is the GF180MCU port of management core for Caravel. For more information about the Caravel management SoC, see https://github.com/efabless/caravel_mgmt_soc_litex.

Reference implementation of OGC KML 2.2

Rocket Chip Generator

Random instruction generator for RISC-V processor verification

FuseSoC-based SoC for VeeR EH1 and EL2

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

RISC-V RV64GC emulator designed for RTL co-simulation

Working draft of the proposed RISC-V V vector extension

Processor support packages

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...

Unit tests generator for RVV 1.0

The Scala parser to parse riscv/riscv-opcodes generate

frequency divider tiny tapeout design

This IP block simulates a binary synchronous (parallel) MOD-4 counter. Applications are CPU's, PWM signal generators, etc. It features: - tri-direction (pause, count up, count down) - loadable (use data[3:1], eg. for jump instruction) - synchronous output(at rising edge) with async (ripple) setup of next count) - easy to control, fast and scalable (each 1 bit counter only depends on previous counter)

8 bit CPU optimized for the constraints of tinytapeout

> © Daniel Arevalos, Innovations for High Performance Microelectronics (IHP).

Basilisk is a tapeout of [Cheshire-IHP130-o](https://github.com/pulp-platform/cheshire-ihp130-o) which is an implementation of the [Cheshire SoC platform](https://github.com/pulp-platform/cheshire) in IHP130 using only open-source tools from RTL to GDS.

EE 628 (University of Hawaiʻi at Mānoa) https://github.com/bmurmann/EE628

See [doc/README.md](doc/README.md)