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Analog / Mixed-Signal IC Engineer

PhD candidate at NOVA-UNL / TU Delft

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Hi! My name is Diogo André. I'm currently pursuing a PhD in Nanoelectronics under a mixed-scholarship at NOVA University of Lisbon, School of Science and Technology (Monte da Caparica, Portugal), and TU Delft, Bioelectronics Group (Delft, The Netherlands). I'm specialising in Analog / Mixed-Signal IC Design, focusing on Analog Front-Ends and Quantizer ASIC Interfaces for Ultrasound Imaging Transducer Arrays. I am also a big fan of using C-lang and Python to develop my own tools for automatic layout design and custom extractors for parasitic passive lumped elements and crosstalk between signal lines. Feel free to contact me!

📂 Personal Info

📅 Nov 19, 1998
🏠 R. Bento Gonçalves 68, 2835-674 Barreiro, Portugal
E-mail: 📧 das.dias@campus.fct.unl.pt 📧 ddias@tudelft.nl
🔗 Google Scholar
🔗 GitHub
🔗 LinkedIn

🎓 Education

MSc. in Electrical and Computers Engineering

NOVA University of Lisbon (Sep 2019 - Dec 2021)
Grade: 17/20

BSc. in Electrical and Computers Engineering

NOVA University of Lisbon (Sep 2016 - Jul 2019)
Grade: 17/20

🏢 Experience

CMOS Process Development Kits (PDKs)

28 nm (HPC+) TSMC PDK, 130 nm UMC PDK

PhD Candidate (ASICs For Ultrasound Image-Guided Vagus Nerve Stimulation)

NOVA University of Lisbon, Delft University of Technology (May 2022 - Ongoing)

Nyquist Data-Rate Converters Course (Teaching Assistant)

Delft University of Technology (Feb - May 2024)

Erasmus+ Traineeship Student

Delft University of Technology (Feb - Jun 2021)
- Master Thesis Dissertation

Electronics II Course (Teaching Assistant)

NOVA University of Lisbon (Sep - Dec 2019)

📚 Research

A PVT-Robust Open-loop Gm-Ratio× 16 Gain Residue Amplifier for> 1 GS/s Pipelined ADCs

CTS, LASI, NOVA University of Lisbon (Dec 2023)
- IEEE ISCAS ’24 Publication

A Parasitic Resistance Extraction Tool Leveraged by Image Processing

PDEEC, NOVA University of Lisbon (Dec 2021)
- IEEE ISCAS ’22 Publication

Preliminary Assessment of an Ultrasonic Level Sensor for the Calorimetric Measurement of AC Losses in Superconducting Devices

CTS, NOVA University of Lisbon (Sep 2020 - Sep 2021)
- YEF-ECE ’22 Publication

Ultrasound-based Cryogenic Monitoring System for Superconducting Systems

CTS, NOVA University of Lisbon (Sep 2020 - Sep 2021)
- EUCAS ’21 Publication

🛠️ Technical Skills & Tools

  • Cadence - Analog / Mixed-Signal Base-Band & RF IC Design
  • Cadence / KLayout / Python - IC Layout Design
  • Xillinx ISE - Digital IC Design, Verilog
  • MATLAB, Python, C, Verilog
  • MS Office, Git, LaTeX
  • (Mac) OSX, Linux(Ubuntu/CentOS), Windows

🏆 Certifications

Artificial Intelligence Course

Samsung Innovation Campus at NOVA University of Lisbon (Jun - Sep 2021)

🔬 Projects

novaad

Open-Source Software Contribution
- A Python tool for Look-up Table (LUT)-based Gm/Id Analog IC design.

gdsfactory/gplugins/spice

Open-Source Software Contribution
- A Python library for converting between YAML Markup language and SPICE schematic netlist description language.
This tool explores the use of modern computer Markup language YAML to represent schematic netlists, allowing for integrated photonic and electronic schematics to co-exist and relate to each other in a single human-readable file. YAML has also readily available Serializer/Deserializer parsers for most common programming languages (C++, C, Python, Ruby, Go, ...).

  • Important Note: both the base source code for the gdsfactory/gplugins/spice and gdsfactory/gplugins/vlsir tools were initially aggregated into a personal repository of mine - parcirc.

gdsfactory/gplugins/vlsir

Open-Source Software Contribution
- A Python library for converting between Klayout's DB Netlist format and other electrical schematic file formats (SPICE, Spectre, Xyce)
- More about the tool at: gdsfactory.github.io/gplugins/notebooks/vlsir_netlist
This work is supported and inspired by Dan Fritchman's VLSIR Tools work, linking the way PDK information is represented in the older, closed-source custom filesystem formats to new, open-source, supported and maintained file and binary formats that allow for a greater information compression and inter-programming language data-structure sharing and interpretation through the use of Google's Protobuf data interface protocol. I highly encourage you to read more about Dan Fritchman's work.

Master Thesis Dissertation

NOVA University of Lisbon & Delft University of Technology (Sep 2020 - Dec 2021)
- "On the Use of Image Processing for 3D Parasitic Resistance Networks Extraction in Integrated Circuits"
- Grade: 19/20

Zero-IF FSK RF Receiver Analog Front-End

NOVA University of Lisbon (Sep - Dec 2020)
- Designed in 0.13µm (MM/RF) UMC technology

120 dB Gain, Low-Voltage (0.9 V supply) Operational Transconductance Amplifier

NOVA University of Lisbon (Sep - Nov 2020)
- Designed in 0.13µm (MM/RF) UMC technology

66 dB Gain, 100 MHz GBW Fully-Differential Hybrid Telescopic-Folded Cascode Amplifier

NOVA University of Lisbon (Nov - Dec 2019)
- Designed in 0.13µm (MM/RF) UMC technology

🌍 Languages

  • Portuguese: ○ ○ ○ ○ ○
  • English: ○ ○ ○ ○ ○
  • Spanish: ○ ○ ○
  • Dutch: ○ ○

🎭 Extra-Curricular Activities

Pedagogical Committee Representative

NOVA University of Lisbon (Nov 2019 - Jul 2021)
- Electrical and Computers Engineering Department

Volunteer Work – Refood Telheiras, Lisbon

Sep - Dec 2019
- Redistribution of food waste

🎨 Hobbies

  • Reading and watching documentaries about History
  • Electric Bass Guitar
  • Half-Marathon Running
  • Contributing to open-source EDA-CAD software